Download key generator for Quartus II Sp1 Altera Complete Design Suite v11.0.208
- Support for GigE modes and SDI embedded transceivers;
- Now support setting additional transceivers. parameters (receiver offset calibration, linear equalizer, and dynamic reconfiguration of PMA analog settings).
Added debugging interface to external memory chips (Memory Interface Toolkit). The new tool reportedly allows real-time monitor the effectiveness of the memory subsystem. You can find the most efficient mode of operation of the memory controller, changing its configuration.
Added debugging tool for the transceiver (Transceiver Toolkit). Improved interface channel manager allows real-time link to watch the status of receivers and transmitters. Enhanced control panel lets the channels on the fly to change the parameters of transceivers and see how it affects the system. All this enables developers to rapidly create and debug board.
There was a better means of rapid establishment of the project rather than QSys SOPS Builder. Allows you to quickly connect QSys-compliant IP-Cores blocks into a single system.
+ Improved Chip Planner (transceiver settings for Stratix V FPGA);
+ Added support for 64-bit Windows and Linux for DSP Builder
+ Added another IP Core - Deinterlacer II IP core
+ Improved support for Cyclone IV GX FPGAs and MAX V CPLDs (see final timing model can be generated and the POF).
+ Improved the last problem with the Cyrillic alphabet in a text editor))
Bit depth: 32bit +64 bit
System Requirements: OS: Windows 2000 / XP / Vista / 7
10 Gb Disk Space
2 Gb RAM (recommended)
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