Download key generator for Modelsim SE 10.1c x86/x64
The system of digital simulation projects based on VHDL, Verilog and "mixed" descriptions with built-in performance analysis, indicating "active" code (code coverage), the comparator time diagrams and visualizer Enhanced Dataflow Window. Main features: high speed simulation for RTL and Gate projects; single simulator kernel and optimized architecture Native Compiled; interactive debugging and analysis with a module Debug Detective; integrated analysis of Code Coverage; optimization of simulation speed by using the Performance Analyzer Performance Analyzer; comprehensive tracing signals Signal Spy; integrated debugger C, C and interfaces support Tcl / Tk; support for OS Unix / Windows / Linux.
The basic functionality of
Record high speed compilation and simulation. A single "core" of the simulation. The possibility of modeling "mixed" VHDL / Verilog-projects on a common "core". Ease of portability and support for libraries through the independence of the platform and version of the simulator. Protection of "intellectual property", which are guaranteed by compiling machine-independent object code. Extensive debugging capabilities. Simple and full-featured graphical user interface. Easy configuration to individual user requirements using Tcl / Tk. Paul
tion supports all standard VHDL and Verilog. Runtime libraries support all major manufacturers of ASIC and FPGA. Integration with packages of other firms. Technical Support Mentor Graphics. ModelSim SE / PLUS allows the user to "mix" VHDL-Verilog-and the objects within a project, enabling a "through" debug the project.
Bit depth: 32bit +64 bit
Compatibility with Vista: complete
Compatible with Windows 7: complete
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